1. Field of the Invention
The present invention relates to a method and apparatus for transferring data between systems running at different clock rates. More specifically, the present invention relates to simplifying the flag control circuitry of a first in first out memory buffer which transfers data between a source system running at one clock rate, and a destination system running at a different clock rate.
2. Description of Related Art
A First-in, first-out (FIFO) buffer or memory unit can be used to temporarily store information for transfer between two circuits running at different clock rates. Separate input and output terminals on the FIFO allow data to be input into the FIFO at one clock rate and output from the FIFO at a different clock rate. Thus when placed between a source unit and a destination unit running on two different clock rates, the FIFO can match data flow between the two units by accepting data from a source unit at one rate of transfer and delivering data to a destination unit at a different rate. In particular if the source unit is slower than the destination unit, the FIFO can be filled with data at a slower rate and later emptied at a higher rate. Conversely, if the source unit is temporarily faster than the destination unit, the FIFO may store the bursts of data and output the data in the time interval between bursts.
Limited memory size requires that the aggregate data transferred into the FIFO and the aggregate data removed from the FIFO be approximately equivalent. Thus if the cumulative input of data into the FIFO significantly exceeds the cumulative output of data by the FIFO, memory overflow can result. Conversely, if the cumulative output of data from the FIFO exceeds the cumulative inflow of data over a significant period of time, memory underflow or the emptying of the FIFO memory and the output of invalid data may result. Thus to prevent either of these conditions from occurring, conventional asynchronous FIFOs use flag circuitry to indicate their status.
Conventional flag circuitry includes logic which continuously compares the values of the input and output data pointers and indicates when they are close (FIFO emptying) or distant (FIFO filling). Copies of the input (write) and output (read) pointers are synchronized and continuously compared. The comparison logic in the flag circuitry provides flexible status information, which may include multiple threshold information, as well as indicators which warn when the FIFO is empty or when the FIFO is full.
The primary problem with current flag circuitry is that complex comparison circuitry is required. The comparators themselves are complicated logic. Synchronization logic which enables comparison between the two time domains also adds to circuit complexity. In small FIFOs the complexity of the overhead logic is excessive.
Larger circuits suffer less from the overhead created by conventional flag circuitry because the increase in number of logic elements in a comparator and synchronization logic circuit is proportional to the base-2 logarithm of the FIFO size. The slow increase in computational requirements makes conventional FIFO flag logic acceptable for large FIFOs; however, in small FIFOs the complexity of the comparators and synchronizers can significantly exceed the complexity of the FIFO RAM and pointers. Small FIFOs are commonly used in video systems where close synchronization between different clocks make large FIFOs unnecessary
The complicated circuitry used to generate control flags for large FIFOs requires significant resources and is inefficient, particularly in applications where small FIFOs are used. Thus a simple and reliable flag control method for use in small FIFO memories is needed.